As is known, a solid electrolytic capacitor is used for canceling a noise generated from a device such as a CPU or stabilizing a power supply system for an electronic apparatus. FIG. shows the solid electrolytic capacitor disclosed in the Patent Document described below. The illustrated solid electrolytic capacitor X includes a porous sintered body made of metal having valve action (hereinafter simply referred to as “valve metal”). An intered body 90. The anodeanode wire 91 is provided to be partially embedded in the porous s wire 91 has a portion projecting from the porous sintered body 90, and the projecting portion serves as an internal anode terminal 91a. A conductive resin film 92 is formed on the porous sintered body 90 to serve as a cathode. Conductive members 93 and 94 are electrically connected to the internal anode terminal 91a. and the conductive resin 92, respectively. The conductive members 93 and 94 include portions exposed on the protective resin 95, and the exposed portions serve as an external anode terminal 93a and an external cathode terminal 94a for external connection. For noise cancellation and stabilizing the power supply system, the high-frequency characteristics of the solid electrolytic capacitor X needs to be enhanced.
Patent Document 1: JP-A-2003-163137
Generally, the frequency characteristics of impedance Z of a solid electrolytic capacitor are determined by the following formula 1.Z=√{square root over ((R2+(1/ωC−ωL)2))}(ω: 2πf(f: frequency), C: Capacitance, R: Resistance, L: Inductance)   [Formula 1]
As will be understood from the above formula, in a frequency region lower than the self-resonant frequency, 1/ωC is determinant. Therefore, in this frequency region, the impedance can be reduced by increasing the capacitance of the solid electrolytic capacitor. In a frequency region near the self-resonant frequency (high frequency region), the resistance R is dominant. Therefore, to reduce the ESR (equivalent series resistance) of the solid electrolytic capacitor is desirable. Further, in an ultra high frequency region higher than the self-resonant frequency, ωL is dominant. Therefore, the ESL (equivalent series inductance) of the solid electrolytic capacitor needs to be reduced.
Also in the conventional solid electrolytic capacitor X, various measures are taken to reduce the ESR and ESL. Specifically, to reduce the ESR and ESL, the shape of the porous sintered body 90 or the shape of the node wire 91 is improved, or the material of a solid electrolytic layer formed in the porous sintered body 90 is improved.
However, since recent CPUs tend to have a higher clock number, a noise including a higher frequency component tends to be generated. Further, in accordance with a speed increase and digitalization of electronic devices, a power supply system capable of responding at high speed is needed. Therefore, with respect to a solid electrolytic capacitor used for such a purpose, further reduction of ESL is demanded.
Under such circumstances, the above-described solid electrolytic capacitor X has the following problem. Although the shapes of the porous sintered body 90 and the anode wire 91 are improved to reduce the inductances, the inductances of other parts (e.g. conductive members 93, 94) are not reduced. Therefore, such a structure cannot sufficiently fulfill the demand for a low ESL. Thus, in the solid electrolytic capacitor X, there is still room for improvement with respect to the reduction of the ESL of the entire device.